{"id":97907,"date":"2026-04-07T15:06:40","date_gmt":"2026-04-07T06:06:40","guid":{"rendered":"https:\/\/layla-hr.com\/semi\/97907\/"},"modified":"2026-04-07T15:06:40","modified_gmt":"2026-04-07T06:06:40","slug":"sr-staff-engineer-compiler","status":"publish","type":"post","link":"https:\/\/layla-hr.com\/semi\/97907\/","title":{"rendered":"Sr Staff Engineer, Compiler"},"content":{"rendered":"","protected":false},"excerpt":{"rendered":"","protected":false},"author":2,"featured_media":0,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[66,112,86],"tags":[136],"area":[13,15],"income":[102,103,104],"checked_slug":[],"class_list":{"0":"post-97907","1":"post","2":"type-post","3":"status-publish","4":"format-standard","6":"category-catsub05","7":"category-other","8":"category-catsub25","9":"tag-136","10":"area-area11","11":"area-area13","12":"income-income01","13":"income-income02","14":"income-income03","15":"entry_article"},"acf":{"company":"\u30eb\u30cd\u30b5\u30b9 \u30a8\u30ec\u30af\u30c8\u30ed\u30cb\u30af\u30b9\u682a\u5f0f\u4f1a\u793e","jobtitle01":"Sr Staff Engineer, Compiler","jobtitle02":"","jobdescription01":"Job Description\n\n\n\nAs an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads \u2014 from perception and sensor fusion to in-vehicle assistants and advanced driver assistance \u2014 are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.\nThis role bridges software compiler development, AI model lowering\/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications..\n\n\u3010Job Description\u3011\n\u30fbLead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration\n\u30fbDesign and implement graph\u2011level optimizations (operator fusion, quantization\u2011aware rewrites, memory\u2011aware scheduling, partitioning)\n\u30fbDrive performance optimization for target NPUs, including tiling, tensor layout, and multi\u2011core execution strategies\n\u30fbPartner with SoC and AI accelerator architects to influence hardware features through compiler insights\n\u30fbOwn performance KPIs for real automotive AI workloads using simulators, profilers, and silicon\u2011correlated models\n\u30fbEnsure compiler outputs meet automotive requirements (real\u2011time behavior, determinism, quality expectations)\n\u30fbMentor senior engineers and set technical direction without people\u2011management responsibilities\n\n\u3010Impact & Differentiators\u3011\nRenesas\u2019 Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards. \u00a0An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric \u2014 directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.\n\n\n\nQualifications\n\n\n\n\u3010Must-Have\u3011\n\u30fbMS\/PhD (or equivalent experience) in Computer Science, EE, or related field\n\u30fbDeep experience building AI compilers, accelerator backends, or graph optimization frameworks\n\u30fbStrong expertise in graph optimization and performance optimization for NPUs or custom accelerators\n\u30fbExperience with MLIR, LLVM, TVM\u2011like systems, or proprietary compiler IRs\n\u30fbExcellent C\/C++ and Python skills\n\u30fbSolid understanding of AI inference workloads (CNNs, transformers, perception or generative models)\n\u30fbStrong communication skills are required, e.g. agile development experience in Scrum team (Scrum Master or member)\n\n\u3010Nice-to-Have\u3011\n\u30fbExperience with automotive or safety\u2011critical systems\n\u30fbBackground in heterogeneous SoCs (CPU\/GPU\/DSP\/NPU)\n\u30fbPerformance modeling or hardware\u2013software co\u2011design experience\n\n\n\nAdditional Information\n\n\n\n\u30eb\u30cd\u30b5\u30b9\u306f\u3001\u300cTo Make Our Lives Easier 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