{"id":97419,"date":"2026-04-03T09:08:00","date_gmt":"2026-04-03T00:08:00","guid":{"rendered":"https:\/\/layla-hr.com\/semi\/97419\/"},"modified":"2026-04-03T09:08:00","modified_gmt":"2026-04-03T00:08:00","slug":"arm-cpu-subsystem-design-engineer","status":"publish","type":"post","link":"https:\/\/layla-hr.com\/semi\/97419\/","title":{"rendered":"ARM CPU Subsystem Design Engineer"},"content":{"rendered":"","protected":false},"excerpt":{"rendered":"","protected":false},"author":2,"featured_media":0,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[66,63,91],"tags":[136],"area":[13,15],"income":[102,103,104],"checked_slug":[],"class_list":{"0":"post-97419","1":"post","2":"type-post","3":"status-publish","4":"format-standard","6":"category-catsub05","7":"category-catsub02","8":"category-catsub30","9":"tag-136","10":"area-area11","11":"area-area13","12":"income-income01","13":"income-income02","14":"income-income03","15":"entry_article"},"acf":{"company":"\u30eb\u30cd\u30b5\u30b9 \u30a8\u30ec\u30af\u30c8\u30ed\u30cb\u30af\u30b9\u682a\u5f0f\u4f1a\u793e","jobtitle01":"ARM CPU Subsystem Design Engineer","jobtitle02":"","jobdescription01":"Job Description\n\n\n\n\u3010Background of the Recruitment\u3011\n\nWith the advancement of automotive electrification and intelligence, automotive SoCs have become a critical technology that shapes vehicle value.\nThe R-Car series has steadily evolved as a large\u2011scale, high\u2011function automotive SoC by integrating a wide variety of IPs, including CPU, memory, high\u2011speed interfaces, AI\/video, functional safety, and security.\nOur organization develops SoC IPs through a combination of in\u2011house IP development and the integration of third\u2011party IPs, with the CPU subsystem playing a central role in overall system performance.\nWorking on large\u2011scale and technically demanding SoC development provides opportunities to gain broad experience across design, verification, and architectural studies.\nWe welcome engineers who are eager to deepen their expertise through CPU subsystem development and grow into future technical leaders within our organization.\n\n\u3010Job Description\u3011\n\nContribute to the development of the CPU subsystem for automotive SoCs (R-Car series), covering key components such as CPU cores, cache architecture, memory\u2011related areas, and bus\/interconnect logic.\nParticipate in specification review, logic design, verification, debugging, and evaluation activities, taking responsibility for assigned development areas.\nWork on both in\u2011house IPs and third\u2011party IPs (e.g., CPU cores, cache or related components), including integration, parameter adjustment, and technical issue resolution.\nTake part in design reviews and defect analysis, providing technical input and supporting quality improvement of the overall subsystem.\nCollaborate with development teams in Japan, India, and Vietnam, contributing within a global, multi\u2011site development environment.\n\n\u203bThe full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process.\n\n\n\nQualifications\n\n\n\n\u3010MUST\u3011\n\nHands\u2011on experience in digital design or verification for SoC or IP development\n(e.g., RTL design, verification, debugging, specification review, or design review support).\nExperience working with design specifications and technical documentation to carry out design and\/or verification tasks.\nAbility to collaborate with engineers and stakeholders and address technical issues through discussion and analysis.\nAbility to read and write technical documents in English, or willingness to work in a global development environment using English.\n\n\u3010WANT\u3011\n\nExperience in one or more of the following areas: CPU, cache architecture, memory\u2011related logic, or bus\/interconnect design or verification.\nExperience with third\u2011party IP integration, including constraint clarification, configuration, or technical issue handling.\nKnowledge of power domain separation and physical implementation considerations (e.g., P&R).\nExperience in defect analysis, root\u2011cause investigation, and countermeasure discussion in SoC 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