{"id":97418,"date":"2026-04-03T09:07:53","date_gmt":"2026-04-03T00:07:53","guid":{"rendered":"https:\/\/layla-hr.com\/semi\/97418\/"},"modified":"2026-04-03T09:07:53","modified_gmt":"2026-04-03T00:07:53","slug":"ddr-interface-evaluation-leader-2","status":"publish","type":"post","link":"https:\/\/layla-hr.com\/semi\/97418\/","title":{"rendered":"DDR Interface Evaluation Leader"},"content":{"rendered":"","protected":false},"excerpt":{"rendered":"","protected":false},"author":2,"featured_media":0,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[66,90,74],"tags":[136],"area":[13,15],"income":[102,103,104],"checked_slug":[],"class_list":{"0":"post-97418","1":"post","2":"type-post","3":"status-publish","4":"format-standard","6":"category-catsub05","7":"category-catsub29","8":"category-catsub13","9":"tag-136","10":"area-area11","11":"area-area13","12":"income-income01","13":"income-income02","14":"income-income03","15":"entry_article"},"acf":{"company":"\u30eb\u30cd\u30b5\u30b9 \u30a8\u30ec\u30af\u30c8\u30ed\u30cb\u30af\u30b9\u682a\u5f0f\u4f1a\u793e","jobtitle01":"DDR Interface Evaluation Leader","jobtitle02":"","jobdescription01":"Job Description\n\n\n\n\u3010Background of the Recruitment\u3011\n\nAs automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality.\nThe R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high\u2011speed interfaces, memory, AI\/video, functional safety, and security.\nWithin such SoCs, the DDR interface is a critical component that directly impacts system stability and performance.\nEnsuring reliable operation through silicon\u2011level evaluation, margin analysis, and stress testing is essential, particularly as SoCs become more highly integrated and operate at higher performance levels.\nWe are therefore seeking a technical leader who can leverage hands\u2011on experience in DDR interface evaluation to work closely with design teams and IP vendors, and lead evaluation activities with sound technical judgment.\nThis role is expected to contribute to overall development by using evaluation as a starting point to support quality improvement across the SoC.\n\n\u3010Job Description\u3011\n\nLead the technical execution of DDR interface evaluation for automotive SoCs (R-Car series).\n\u00a0- Target examples include LPDDR4X \/ 5 \/ 5X \/ 6, DDR PHY, and memory\u2011controller\u2011related interfaces.\nDrive silicon and board\u2011level evaluation, margin analysis, stress testing, and compliance with standards and internal guidelines, ensuring the quality and reliability of the DDR interface.\nDefine and align evaluation strategy, design test items and conditions, and consolidate evaluation results into clear outputs.\nWhen issues arise, collaborate with design teams, SoC teams, and IP vendors to perform root\u2011cause analysis and drive countermeasure planning.\nProvide technical leadership to evaluation and design members across Japan, India, and Vietnam, clarifying evaluation flow and decision criteria to improve overall quality.\n\n\u203bThe full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process.\n\n\n\nQualifications\n\n\n\n\u3010MUST\u3011\n\nHands\u2011on experience in evaluation or verification of DDR interfaces (e.g., LPDDR4\/4X\/5).\nExperience in issue analysis, root\u2011cause investigation, and countermeasure discussion based on margin testing and stress evaluation.\nAbility to organize evaluation results and conduct technical discussions and alignment with design teams and stakeholders.\nKnowledge or experience related to analog behavior and characteristics relevant to DDR interfaces (e.g., DDR PHY, PLL, jitter, noise, SI\/PI, power integrity).\nAbility to collaborate technically in English with design sites in India and Vietnam, as well as IP vendors.\n\n\u3010WANT\u3011\n\nExperience leading or co\u2011leading evaluation activities for DDR PHY, memory controllers, or board\u2011level DDR interfaces.\nExperience in measurement and analysis of DDR signals, timing, and power behavior using lab equipment (e.g., oscilloscopes, logic analyzers).\nExperience coordinating with external IP vendors on technical inquiries, issue alignment, and sharing of evaluation results.\nExperience in automotive SoC projects or in products requiring high levels of quality and reliability.\nInterest in expanding contribution beyond DDR evaluation into broader cross\u2011functional collaboration with design and SoC teams.\nJapanese language proficiency at a conversational level\n\n\nAdditional Information\n\n\n\nIf you are interested in this position, please feel free to contact us at the details below:\nRecruiter:Masana Ueno\n\n\u30eb\u30cd\u30b5\u30b9\u306f\u3001\u300cTo Make Our Lives Easier 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experience in evaluation or verification of DDR interfaces (e.g., LPDDR4\/4X\/5).\nExperience in issue analysis, root\u2011cause investigation, and countermeasure discussion based on margin testing and stress evaluation.\nAbility to organize evaluation results and conduct technical discussions and alignment with design teams and stakeholders.\nKnowledge or experience related to analog behavior and characteristics relevant to DDR interfaces (e.g., DDR PHY, PLL, jitter, noise, SI\/PI, power integrity).\nAbility to collaborate technically in English with design sites in India and Vietnam, as well as IP vendors.","area":"\u52e4\u52d9\u5730\n                    \n                    \u5c0f\u5e73\u5e02","salary":"","officehours":"","holiday":"","welfareprogramme":"","url":"https:\/\/career.renesas.com\/job\/ddr-interface-evaluation-leader-in-kodaira-japan-jid-4410","imageurl":"","summary":"\u534a\u5c0e\u4f53\u696d\u754c\u306e\u81ea\u52d5\u8eca\u5411\u3051SoC\uff08System on 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