{"id":97417,"date":"2026-04-03T09:07:45","date_gmt":"2026-04-03T00:07:45","guid":{"rendered":"https:\/\/layla-hr.com\/semi\/97417\/"},"modified":"2026-04-03T09:07:45","modified_gmt":"2026-04-03T00:07:45","slug":"high-speed-serdes-interface-evaluation-leader-3","status":"publish","type":"post","link":"https:\/\/layla-hr.com\/semi\/97417\/","title":{"rendered":"High-Speed SerDes Interface Evaluation Leader"},"content":{"rendered":"","protected":false},"excerpt":{"rendered":"","protected":false},"author":2,"featured_media":0,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[66,73,74],"tags":[136],"area":[13,15],"income":[102,103,104],"checked_slug":[],"class_list":{"0":"post-97417","1":"post","2":"type-post","3":"status-publish","4":"format-standard","6":"category-catsub05","7":"category-catsub12","8":"category-catsub13","9":"tag-136","10":"area-area11","11":"area-area13","12":"income-income01","13":"income-income02","14":"income-income03","15":"entry_article"},"acf":{"company":"\u30eb\u30cd\u30b5\u30b9 \u30a8\u30ec\u30af\u30c8\u30ed\u30cb\u30af\u30b9\u682a\u5f0f\u4f1a\u793e","jobtitle01":"High-Speed SerDes Interface Evaluation Leader","jobtitle02":"","jobdescription01":"Job Description\n\n\n\n\u3010Background of the Recruitment\u3011\n\nAs automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality.\nThe R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high\u2011speed interfaces, memory, AI\/video, functional safety, and security.\nAmong these technologies, high\u2011speed SerDes interfaces such as PCIe and CSI and DP and UCIe play a critical role in overall system performance and reliability.\nAs interface speeds continue to increase and system complexity grows, ensuring quality through thorough silicon\u2011level evaluation and signal integrity verification has become increasingly important.\nIn this context, we are seeking a technical leader who has hands\u2011on experience in high\u2011speed SerDes interface evaluation and can work closely with design teams and IP vendors to lead evaluation activities from a technical standpoint.\nBy taking ownership of evaluation and contributing technical judgment to development, this role is expected to play a key part in improving the overall quality of our automotive SoCs.\n\n\u3010Job Description\u3011\n\nLead the technical execution of high\u2011speed SerDes interface evaluation for automotive SoCs (R-Car series), covering interfaces such as PCIe, CSI, DP, UCIe, SerDes PHY, and other high\u2011speed I\/F as applicable.\nDrive evaluation activities including silicon\/board-level testing, signal integrity\/quality assessment, stress testing, and standards\/compliance confirmation, ensuring interface quality and robustness.\nDefine and align evaluation strategy, organize test items, and consolidate evaluation results into actionable outputs for stakeholders.\nWhen issues occur, coordinate with design teams, SoC stakeholders, and IP vendors to perform triage, root-cause investigation, and countermeasure planning.\nProvide technical leadership to evaluation members across sites and functions, helping establish clear evaluation flow and decision criteria to improve overall execution quality\n\n\u203bThe full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process.\n\n\n\nQualifications\n\n\n\n\u3010MUST\u3011\n\nHands\u2011on experience in evaluation or verification for high\u2011speed interfaces (e.g., SerDes, PCIe, UCIe).\nExperience in issue analysis, root\u2011cause investigation, and countermeasure discussion based on silicon\/board evaluations, signal\u2011quality assessment, and stress testing.\nAbility to summarize results and conduct technical discussions and alignment with design teams and stakeholders.\nKnowledge\/experience related to analog behavior and characteristics relevant to high\u2011speed links (e.g., PLL\/PHY, jitter, noise, SI\/PI).\nAbility to collaborate technically in English with design sites in India and Vietnam, as well as IP vendors.\n\n\u3010WANT\u3011\n\nExperience leading or co\u2011leading evaluation for a specific high\u2011speed interface such as PCIe, CSI, DP, UCIe, or SerDes PHY.\nExperience with high\u2011speed measurement and analysis using tools such as oscilloscopes, BERT, and TDR.\nExperience coordinating with external IP vendors on technical inquiries, issue alignment, and evaluation result sharing.\nExperience in automotive SoC evaluation or in products\/projects with high quality and reliability requirements.\nInterest in expanding contribution beyond evaluation into broader cross\u2011functional collaboration with design and SoC teams.\nJapanese language proficiency at a conversational level\n\n\nAdditional Information\n\n\n\nIf you are interested in this position, please feel free to contact us at the details below:\nRecruiter:Masana Ueno\n\n\u30eb\u30cd\u30b5\u30b9\u306f\u3001\u300cTo Make Our Lives Easier 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experience in evaluation or verification for high\u2011speed interfaces (e.g., SerDes, PCIe, UCIe).\nExperience in issue analysis, root\u2011cause investigation, and countermeasure discussion based on silicon\/board evaluations, signal\u2011quality assessment, and stress testing.\nAbility to summarize results and conduct technical discussions and alignment with design teams and stakeholders.\nKnowledge\/experience related to analog behavior and characteristics relevant to high\u2011speed links (e.g., PLL\/PHY, jitter, noise, SI\/PI).\nAbility to collaborate technically in English with design sites in India and Vietnam, as well as IP vendors.","area":"\u52e4\u52d9\u5730\n                    \n                    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