Optical Engine Chip Architecture and PHY Design Engineer for POI

ASIC/SoC設計

テスト・評価エンジニア

光電子デバイス

Core Technical Expertise Optical Communication System Design Experience with link budget calculations and modeling of link for simulation. Experience with analysis for degradation of optical link and research for compensation. Experience defining required performance on optical devices and components. Understanding modulation method and demodulation algorithm. Chip Architecture for Optical I/O Experience defining architecture for optical engines integrated with ASICs or SoCs. Understanding of co-packaged optics and chiplet-based designs for high-bandwidth interconnects. PHY Design Deep knowledge of high-speed SerDes, PAM4 signaling, and optical PHY layer design. Familiarity with clock-data recovery (CDR), equalization, and link training for optical channels. Parallel Optical Interconnect Expertise in multi-lane optical interfaces (e.g., 400G/800G Ethernet, InfiniBand). Knowledge of optical modulation formats and encoding schemes. Required Experience PoC for Novel Optical Network Architecture Experience with implementation model design. Experience prototyping for transmitter, receiver and link media and system performance evaluation. Integration & Packaging Experience with electrical-optical co-design for chip-to-optical engine integration. Understanding of thermal management and mechanical constraints for optical engines in advanced packaging (e.g., 2.5D/3D IC, silicon interposer). Experience with RF modeling in optical communication systems. Understanding RF degradation factor on link and devices. Modeling & Simulation Proficiency in signal integrity (SI) and power integrity (PI) analysis for high-speed optical PHY. Familiarity with simulation tools: Cadence, Synopsys, Ansys HFSS, Lumerical for photonic modeling. Validation & Testing Hands-on experience with optical PHY bring-up, BER testing, and compliance validation. Knowledge of IEEE and OIF standards for optical interconnects. Experience with requirement analysis for conformance on the technical standard. Collaboration Ability to work across ASIC design, packaging, and optical component teams. Strong documentation and communication skills for architecture specs and design reviews. Industry & Standards Familiarity with CPO (Co-Packaged Optics), PCIe, Ethernet, and InfiniBand standards. Awareness of roadmap trends in optical I/O for AI/HPC systems. Experience making contributions for standardization. PHY design tools Familiarity on the tool for architecture stage, and have breath knowledge on the tools for other design stages. Design Stage and Tools Architecture:　MATLAB/Simulink (system modeling), SystemVerilog/VHDL (RTL architecture) Circuit Design: Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre (DRC/LVS) Simulation: Cadence Sigrity (SI/PI), Keysight ADS, Ansys HFSS, Lumerical, Zemax Verification: Cadence Xcelium, Synopsys VCS, IBIS-AMI models for compliance Testing & Validation: Lab instruments: Keysight Oscilloscopes, BERTs, Optical Power Meters, Components Analyzer, AWG